1. Field of the Invention
Embodiments of the present invention relate generally to memory devices and more specifically to the processing of signals in high speed memory arrays.
2. Description of the Related Art
Electronic systems and devices, such as computers, personal organizers, cell phones, portable audio players, etc., typically include one or more memory devices to provide storage capability for the system. System memory is generally provided in the form of one or more integrated circuit chips and generally includes both random access memory (RAM) and read-only memory (ROM). System RAM is typically large and volatile and provides the system's main memory. Synchronous Dynamic RAM (SDRAM) is a commonly employed type of random access memory.
As will be appreciated, there are a number of different types of SDRAM devices. Early generation SDRAM devices are generally configured such that data from the memory cells may be accessed and one bit of data may be output on every clock cycle. Demands for higher processing speeds led to the development of Double Data Rate (DDR) SDRAM devices. DDR SDRAM devices generally allow for two bits of data to be accessed and output on every clock cycle. To achieve this, DDR SDRAM devices commonly clock data out on every rising and every falling edge of the clock signal.
Typically, the memory cells of a DDR SDRAM memory array are arranged in banks in the array with each cell having an address identifying its location in the array. The array includes a configuration of intersecting rows and columns and a memory cell is associated with each intersection. In order to read from or write to a cell, the particular cell and bank must be selected (addressed). The address for a selected bank is represented by input signals to bank control logic, which may select a bank in response to a particular address. The bank address signals for a conventional configuration of 8 memory banks include three bank address signals, with each combination of signals corresponding to a specific bank. For each operation executed to a bank, the appropriate bank address signals are used to identify the bank. Similarly, to select a cell, a row address and column address may be provided. A row decoder activates a wordline in response to the row address, and a column decoder activates a column decoder output in response to the column address.
Various signals may be used to operate the memory array. For example, a precharge signal may be sent to the memory array to deactivate a row or bank of memory cells before or after a previous or subsequent operation. In some implementations, a Write-with-Autoprecharge command may be given as a write command that automatically performs a precharge operation after completion of the write operation.
In some types of DRAM, such as DDR2 and DDR3, the specification may provide guidelines for the timing of the precharge command. For example, a Write (data) Recovery time (tWR) may be specified. Generally, tWR is referred to as the time necessary to store data into a memory cell before a precharge can occur. More specifically, tWR is the minimum time to guarantee that data in the write buffer can be fully written into a memory cell. If tWR is not satisfied, e.g., if tWR is not sufficiently long enough to store data in a memory cell, then the full data is not stored and a read failure can result.
As memory chips and devices using memory chips become smaller, size of the memory chips and associated logic circuitry, as well as power consumption, may be of increasing importance. Accordingly, it may be desirable to reduce the logic required for tWR precharge circuits for a memory array.
Embodiments of the present invention may be directed to one or more of the problems set forth above.